1. Field of the Invention
The present invention relates to integrated bipolar and complementary metal oxide semiconductor (BiCMOS) devices using silicon-on-insulator (SOI) technology in which the bipolar transistors and the CMOS transistors are fabricated on different surface layers of the SOI substrate. The present invention also provides a method for forming the BiCMOS devices. The structure and method of the present invention overcome topographic challenges as well as providing different surface layers in the SOI substrate for fabricating the various devices present in BiCMOS technology.
2. Background of the Invention
Bipolar transistors are electronic devices with two p-n junctions that are in close proximity to each other. A typical bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, the two p-n junctions, i.e., the emitter-base and collector-base junctions, are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called “bipolar-transistor action.”
If the emitter and collector are doped n-type and the base is doped p-type, the device is an “npn” transistor. Alternatively, if the opposite doping configuration is used, the device is a “pnp” transistor. Because the mobility of minority carriers, i.e., electrons, in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn transistor devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among majority carrier devices, heterojunction bipolar transistors (HBTs) in which the emitter is formed of silicon (Si) and the base of a silicon-germanium (SiGe) alloy have recently been developed. The SiGe alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
The advanced silicon-germanium bipolar and complementary metal oxide semiconductor (BiCMOS) technology uses a SiGe base in the heterojunction bipolar transistor. In the high-frequency (such as multi-GHz) regime, conventional compound semiconductors such as GaAs and InP currently dominate the market for high-speed wired and wireless communications. SiGe BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to the integration of heterojunction bipolar transistors with standard CMOS, yielding the so-called “system on a chip.”
For high-performance HBT fabrication, yielding SiGe/Si HBTs, a conventional way to reduce the base resistance is through ion implantation onto the extrinsic base. The ion implantation will cause damage, however, to the base region. Such damage may ultimately lead to degradation in device performance.
To avoid the implantation damage, a raised extrinsic base (Rext) is formed by depositing an extra layer of polycrystalline silicon atop the conventional SiGe extrinsic base layer. There are essentially two processes that may be applied to achieve such a raised extrinsic base. The first process involves selective epitaxy; the other involves chemical-mechanical polishing (CMP).
In a typical selective epitaxy process, the raised extrinsic base polycrystalline silicon is formed before the deposition of the intrinsic base SiGe. The intrinsic base SiGe is deposited selectively onto the exposed surface of silicon and polycrystalline silicon inside an over-hanging cavity structure. The selective epitaxy with a cavity structure mandates stringent process requirements for good selectivity, and suffers from poor process control. U.S. Pat. No. 5,523,606 to Yamazaki and U.S. Pat. No. 5,620,908 to Inoh, et al. are some examples of prior art selective epitaxy processes.
In addition to selective epitaxy, a raised extrinsic base may be formed by utilizing a CMP process. However, when it comes to SiGe BiCMOS structures, there is a topographic issue for CMP since the CMOS gate creates a thickness difference, which is similar to the gate height (typically 100-250 nm), between the CMOS device area and the bipolar transistor device area. The height of these two device areas must be adjusted to the same level for the raised extrinsic base CMP.
In addition to selective epitaxy, a raised extrinsic base may be formed by utilizing a CMP process. However, when it comes to SiGe BiCMOS structures, there is a topographic issue for CMP since the CMOS gate creates a thickness difference, which is similar to the gate height (typically 100-250 nm), between the CMOS device area and the bipolar transistor device area. The height of these two device areas must be adjusted to the same level for the raised extrinsic base CMP.
In one prior art process; see, for example, U.S. Pat. No. 6,492,238, a BiCMOS having a raised extrinsic base region is formed using a reactive-ion etch (RIE) step to etch part of the film on top of the CMOS gate to make the CMOS transistor and bipolar transistor device areas substantially level. Despite being capable of leveling the two device areas, this prior art approach for adjusting the height differential between the HBT and the CMOS transistor device areas is complicated and requires two additional lithographic levels to achieve leveling between the device areas of the CMOS transistor and the HBT. In addition to the topography challenges in integrating bipolar devices with CMOS devices, there is an ongoing trend in the semiconductor industry for replacing bulk Si technology with SOI technology since SOI permits the formation of high-speed integrated circuits. In SOI technology, a buried insulating layer electrically isolates a top Si-containing layer from a bottom Si-containing layer. The top Si-containing layer, which is oftentimes referred to in the art as the SOI layer, is generally the area in which active devices such as transistors are formed. Devices formed using SOI technology offer many advantages over their bulk Si counterparts including, for example, higher performance, absence of latch-up, higher packing density and low voltage applications. The replacement of bulk Si substrates with SOI is also occurring in BiCMOS devices. In most BiCMOS/SOI structures, the topography challenge mentioned above would also be present.
U.S. Pat. No. 6,232,649 to Lee discloses a process for fabricating a bipolar transistor on an SOI substrate which includes etching a bipolar transistor area into a bottom Si-containing layer of an SOI substrate; in the patented prior art process the etching goes through the top Si-containing layer, the buried insulating layer and an upper surface of the bottom Si-containing layer, stopping somewhere below this upper surface. Despite being capable of fabricating a bipolar transistor on an SOI substrate, this prior art approach needs a selective epitaxial silicon growth process which mandates stringent process requirements for good selectivity, and suffers from poor process control. Moreover, the form factor of the entire prior art bipolar transistors inherently lacks the compactness of the state-of-the art bipolar transistors in advanced BiCMOS technologies, e.g., the entire base region is separated from the collector by oxide sidewalls. This makes it difficult to reduce the product of base-collector capacitance and collector resistance, which is critical to enable fast bipolar transistors.
In addition, the etching used in Lee to form polysilicon sidewalls to connect the buried collectors etches directly into the Si where the buried collector is formed. Not only does this etch create damage in Si, rendering defective epitaxial base layer later on, but also it is not controllable; therefore the depth of the trenches for bipolar transistors formed into the SOI substrate may vary from one area to another as well as vary across a single SOI wafer. This results in a topography problem with each bipolar transistor being formed using technology such as disclosed in Lee.
Another challenge facing BiCMOS device fabrication is that different devices present on the same chip have different substrate requirements. For example, when passive elements such as inductors are present on BiCMOS integrated circuits, it is typically required that the passive elements be formed atop substrates that are highly resistive. A high-resistivity substrate is necessary for high quality factor, high-Q, inductors isolated between digital and analog parts of the circuit.
In view of the state of the art mentioned above, there is a continued need for providing BiCMOS devices that have improved topography between the CMOS device area and the bipolar device area in which SOI technology is used. Additionally, there is a need for being able to tailor portions of the SOI substrate for fabricating passive elements of high quality on the same chip as the bipolar transistors and the CMOS transistors.